Integrated clock gating (ICG), in digital IC designs, is used to reduce power consumption by preventing individual flip flops from switching between logic states when not in use. In integrated clock gating, the flip flops which are not contributing to the functionality of the circuit are selectively inactivated. The ICG cells are activated or inactivated based on certain conditions. The conditions for disabling the clock cells are a design choice. In advanced digital designs, several clock gating cells are used which results in increased power consumption. A comparison of percentage of power consumption between the units in an example IC are logic implementation consuming 29%, flip flops consuming 27%, RAM consuming 18%, clock tree consuming 16% and the ICG consuming 10% of the total power. It is apparent that if the power consumption of one of the aforementioned units can be reduced, the overall power consumption of the IC can be reduced.